Flash memory cells are a type of semiconductor device. Generally, semiconductor devices are very small components, or collections of components, formed on a piece of semiconductor material often referred to as the substrate. Flash memory cells, for example, feature a gate structure formed on the substrate, as will be explained in more detail below. In many current applications, the substrate is a round, thin slice of silicon or some similar material that has been cut from an ingot formed for this purpose. The substrate material is then selectively treated to give it its semiconducting properties.
A semiconductor is a material that conducts electricity only under certain conditions, such as the application of an electrical charge. To make use of this property, various portions of the substrate are treated with impurities such as boron or phosphorus ions. Layers of conductive and insulating material are then added, each layer to be shaped into the tiny structures that form electronic components such as diodes, transistors, and capacitors. These components may then be interconnected to form integrated circuits.
Using current practices, a wafer that may, for example, measure 15-20 cm in diameter is populated with a number, perhaps several dozen dice. Each die, after fabrication, contains thousands if not millions of tiny interconnected electrical components. When formation of these components is largely complete, the dice will be separated from each other to be packaged and used individually. External connections are provided for so that that the integrated circuits on each packaged die may be used for its intended function.
One such function is memory. A memory device includes a collection of components that may be placed in one or more electrical states that represent a certain value. Individual components in semiconductor memory devices may be placed in a state representing either a logical one or a zero. Collections of such devices, however, may be used to represent a much wider range of values. These values can be read and, often, changed repeatedly to a different value. There are several types of semiconductor-based memory devices.
The different types of memory device may be characterized by function, with each device naturally having a structure and composition operable to perform this function. Random access memory (RAM) involves an array of memory devices that are individually programmable to represent given values. In a RAM device, these values may be changed continually within the operational parameters of the system. Read-only memory (ROM) devices are programmed to contain specific values that may then be read, for example, when an electronic appliance is turned on, but programmed values may not be changed.
This is now true only in a sense, however, as more-recently developed devices, although traditionally referred to as ROM, may be reprogrammed, that is, provided with different values than those that were initially set. An EEPROM (electronically-erasable read only memory), for example, stores values in an array of cells that may be reprogrammed by erasing the contents (value) of one or more cells and re-programming the value stored in each cell. Note the word “electronically” simply refers to the fact that an erase operation is performed by application of an electrical charge. (Other methods, for example, include exposure to light of a certain quality.) It is also noted that the EEPROM is not, strictly speaking, a “read-only” type of memory device; the nomenclature simply reflects that it evolved from earlier designs that were, and the distinction often has little relevance.
One type of EEPROM memory device is referred to as a flash memory device. A flash memory is useful because, although an array of cells store values individually, they can by design be erased in blocks for reprogramming if desired. This greatly increases the operating speed of the device. The present invention, as mentioned above, relates to the structure and fabrication of flash cells. A short description of their operation and traditional structure follows.
FIG. 1 is a simplified schematic diagram illustrating an exemplary flash cell 10. Flash cell 10 is formed on substrate 15, in which a source region 16 and a drain region 18 have been created by the doping process. A gate structure 20 includes a floating gate 22 disposed above the substrate is between the source region 16 and the drain region 18, but physically separated from them by an oxide layer 21. The floating gate 22 is formed of, for example polycrystalline silicon (“poly”) or some other conductive material. The oxide layer 21 may be formed of, for example, silicon dioxide (SiO2). A control gate 24 is disposed above the floating gate 22, the two gates being separated by a thin oxide layer 23. In this example, the control gate 24 is coupled to an external electrical connector called a wordline 26. A bit line 28 is coupled to the drain region 18; the source region 16 is connected to ground.
In operation, the charge passing through floating gate 22 is monitored by a cell sensor and, when a sufficient charge is allowed to pass, indicates a logical one. If a negative charge is allowed to accumulate on the floating gate, it acts as a barrier and the charge passing through drops, causing the flash cell 10 to be read as a logical zero. A sufficient voltage applied to the wordline 26, and hence control gate 24, however, clears the accumulated charge and permits the flash cell 10 to return to a logical one state—erasing its contents. Wordline 26 may be coupled to a great many cells like flash cell 10, permitting them all to be erased at the same time.
The structure of another exemplary flash cell is shown in FIG. 2. FIG. 2 is a side view of a flash cell 40, illustrating this exemplary semiconductor device in cross-section. In this example, flash cell 40 includes two gate structures 30 and 50 formed on substrate 44. Each gate structure is, in this view, a mirror image of the other. Gate structure 30 includes a floating gate 32 and a control gate 34 separated by oxide layer 33. A dielectric layer 35 is disposed directly on control gate 34. Similarly, gate structure 50 includes a floating gate 52 separated by oxide layer 53 from control gate 54 and features a dielectric layer 55 disposed over control gate 54.
Erase gate 49 is positioned between gate structure 30 and gate structure 50, and is disposed above oxide structure 48, which is an expanded portion of oxide layer 45. Vertical dielectric spacers 38 and 58 separate gate structures 30 and 50, respectively, from erase gate 49. As should be apparent, in operation a voltage applied to erase gate 49 erases both gate structure 30 and gate structure 50. Erasure may also be performed on only one of gate structures 30 or 50 using wordline structures 36 or 56, respectively. Wordline structure 36 is physically separated from gate structure 30 by spacer 31, and wordline structure 56 from gate structure 50 by spacer 51. Spacers 39 and 59 are disposed on the exterior of wordline structures 36 and 56, respectively. In the flash cell 40, there is a common source region 43, and two drain regions; drain region 41 associated with floating gate 32 and drain region 42 associated with floating gate 52.
In FIG. 2, also shown are the electrical contacts associated with various elements of the flash cell 40. These contacts are typically metal and provide a location for making reliable electrical connections. Here, contacts 37, 47, and 57 serve, respectively, wordline structure 36, erase gate 49, and wordline structure 56. The flash cell 40 is fabricated in a series of steps, which will be briefly described as background to explaining the present invention. FIG. 3 is a flow diagram illustrating a typical method 60 of fabricating a flash memory cell such as flash cell 40 shown in FIG. 2. In this example, a substrate is doped (step 62) with the appropriate impurities to create a source and drain regions. Naturally, more than one type of dopant application may be required, and if so, they will not typically be done at the same time. These source and drain regions may also be formed later in the process; a single step is recited here for purposes of simplicity. An oxide layer is then formed (step 64). This will typically be deposited over the entire wafer surface, and then the undesirable portions will be removed in a selective etching process (not shown).
To fabricate the gate structure (see FIG. 2), a floating gate layer is formed (step 66), for example of poly, followed by a layer of oxide or some other dielectric (step 68), and a control gate poly layer (step 70). A dielectric layer is then formed (step 72) on the control gate poly layer 70. Again, any of the material layers recited in this basic process may include more than one sub layer, and these sub-layers, if present, will likely be formed in separate process steps (not shown). A photoresist layer is then formed and patterned (step 74) for selective etching.
An etching process is then performed (step 76), leaving only the protected gate structures. The remaining photoresist is then removed (step 78). Spacers may be formed (step 80) at this time, using a similar deposition and selective etching technique (steps not separately shown). Another poly layer is then deposited to form the erase gate and wordline structures (step 82). Additionally, spacers outside the wordline structures are added (step 84), and contacts formed (step 86) on the appropriate gates. The contacts are typically metal structures added to facilitate the termination of electrical connections to various parts of the device. The resulting flash cell is illustrated in FIG. 2.
Although adequate, this method and structure have disadvantages in certain applications. For example, in designs that use very small structures, for example having critical dimensions of approximately 90 nm, there remains only a narrow etching process window for spacer etching. In addition, with such small nodes, reverse tunneling performance problems may also become significant. Needed, therefore, is a flash cell structure and fabrication method that tends to widen the spacer-etching window and improve RTV performance. The present invention provides just such a solution.